This work presents the first 32-Gb/s/lane UCIe-S– compliant die-to-die PHY in 22-nm FinFET CMOS. The 32-Gbps/lane, 16-lane transceiver achieves 0.828-Tbps/mm shoreline density and, over a 25-mm organic package channel, achieves an aggregate 0.52-UI eye opening at BER=1e-12 (extrapolated 0.47-UI at BER=1e-15). The transceiver also demonstrates extended operation to 40Gb/s, achieving 0.44-UI eye opening at BER=1e-12 (extrapolated 0.37-UI at BER=1e-15). Supply-scalable circuit innovations enable achieving a 25-mm UCIe-S link energy efficiency of 0.58pJ/bit (0.73pJ/bit) at 32Gb/s/lane (40Gb/s/lane).