Effect of Thermal Boundary Resistance between the Interconnect Metal and Dielectric Interlayer on Temperature Increase of Interconnects in Deeply Scaled VLSI

Temperature increase in the continuously narrowing interconnects accelerates the performance and reliability degradation of very large scale integration (VLSI). Thermal boundary resistance (TBR) between an interconnect metal and dielectric interlayer has been neglected or treated approximately in conventional thermal analyses, resulting in significant uncertainties in performance and reliability. In this study, we investigated the effects of TBR between an interconnect metal and dielectric interlayer on temperature increase of Cu, Co, and Ru interconnects in deeply scaled VLSI. Results indicate that the measured TBR is significantly higher than the values predicted by the diffuse mismatch model and varies widely from 1 × 10-8 to 1 × 10-7 m2 K W-1 depending on the liner/barrier layer used. Finite element method simulations show that such a high TBR can cause a temperature increase of hundreds of degrees in the future VLSI interconnect. Characterization of interface properties shows the significant importance of interdiffusion and adhesion in TBR. For future advanced interconnects, Ru is better than Co for heat dissipation in terms of TBR. This study provides a guideline for the thermal management in deeply scaled VLSI.