低压差调节器
CMOS芯片
计算机科学
电子工程
逻辑门
跌落电压
电压调节器
电气工程
功率(物理)
物理
线性调节器
电压
稳健性(进化)
控制理论(社会学)
调节器
线路调节
时钟发生器
作者
Seong Jin Yun,Jiseong Lee,Yun Chan Im,Yong Sin Kim
出处
期刊:IEEE Transactions on Very Large Scale Integration Systems
[Institute of Electrical and Electronics Engineers]
日期:2019-06-26
卷期号:27 (10): 2237-2245
被引量:2
标识
DOI:10.1109/tvlsi.2019.2920910
摘要
Conventional capless digital low-dropout (DLDO) regulators adopt either a high-speed clock or the burst mode at the expense of a larger quiescent current in order to overcome the degradation of the load transient response caused by the absence of an external capacitor, which causes high power consumption. In this paper, a capless DLDO regulator with a self-clocking burst logic for ultralow power applications is proposed. The self-generated clock in the burst mode of the proposed burst logic is activated temporally in order to achieve both faster load transient response and lower quiescent current. The proposed DLDO regulator is implemented in 14-nm FinFET CMOS technology. The quiescent current and figure-of-merit (FoM) of the proposed DLDO regulator are $0.69~\mu \text{A}$ and 0.097 ps, respectively, with an active area of 0.0035 mm2, excluding a 0.1-nF integrated output capacitor.
科研通智能强力驱动
Strongly Powered by AbleSci AI