Analysis and Design of a Large Dither Injection Circuit for Improving Linearity in Pipelined ADCs

In this paper, a new large dither injection technique is proposed for improving linearity in pipelined analog-to-digital converters (ADCs), without losing the dynamic range of the ADCs and deteriorating the corresponding amplifier’s linearity. First, analyses of a proper pipelined ADC’s architecture are performed for large dither injection. Then, a 9-bit capacitive digital-to-analog converter (DAC) with split architecture is developed to inject the dither ranging from −511/1024 least significant bit (LSB) to 511/1024 LSB of the first stage. To counteract the consumption of the correction range by the capacitive injection dither, the novel 6-bit complementary DACs embedded in the comparator threshold generation circuit are proposed to realize comparator dither injection. In addition, the dither injection amplitude is configurable for investigating different amplitude’s effects on the linearity of the ADC. Finally, the proposed dither injection circuit, together with a 16-bit 150 million samples per second (MSPS) ADC, is implemented in a 0.18- $\mu \text{m}$ CMOS technology. The measured results demonstrate the effectiveness of the proposed techniques. The optimum dither is the 9-bit dither, improving not only the spurious free dynamic range (SFDR) of the small signal by at least 13 dB but also that of the large signal by more than 8 dB compared to the case without dither injection. Moreover, dither injection makes the noise floor clean.