Wafer Warpage Experiments and Simulation for Fan-Out Chip on Substrate

Fan-out chip on substrate (FOCoS) is defined as the fan-out package flip-chip mounts on high pin counts ball grid array substrate. 12-inch advanced wafer level package (aWLP) process is implemented on FOCoS for cost saving advantage. The fan-out package constructs from multi-chips with short interconnection between die to die (D2D) by re-distribution layer (RDL) process, which has the potential for high speed communication and multi-function application. In this paper, a 45×45 FOCoS package size with interconnection between two large size D2D area by three metal layers RDL process is presented. Wafer level warpage control is critical in large size fan-out package of FOCoS. Warpage performance of FOCoS is examined by advanced warpage metrology analyzer (WMA) and finite element model (FEM) in this report. 12-inch mold wafer warpage is dramatically changed through multi-RDL processes. The reliability performance of FOCoS is also evaluated to show the qualification of mass production.