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Design Methodology of a Voltage Bandgap Reference with High PSRR in Advanced Technology Nodes for LDO Application

电源抑制比 带隙基准 共栅 电压基准 电子工程 电气工程 计算机科学 电容器 低压差调节器 电压 温度系数 CMOS芯片 跌落电压 工程类 放大器 晶体管
作者
Robert Leemar M. Bagundol,Jefferson A. Hora,Emrys Leowhel Oling
标识
DOI:10.1109/hnicem57413.2022.10109433
摘要

This paper presents and details a generalized approach in designing a voltage bandgap reference developed in advanced technology nodes. As circuits for different devices keeps on scaling down, contrasting fabrication technologies are developed. This is for the purpose of optimizing distinct design parameters while keeping in check the tradeoffs involved. This in turn keeps pushing the boundaries of integrated circuit design. The voltage bandgap reference is one of many important circiuts that is being integrated to many circuit topologies. Its ability to be temperature-independent is a valuable asset to other circuit blocks like low-dropout volage regulators as well as in devices which incorporate wireless technologies and ADC subsytems. Different subblocks of the voltage bandgap reference, such as the cascode current mirror, operational amplifier, and start-up circuit, are investigated. Its Power Supply Rejection Ratio or PSRR is closely monitored and improved through the use of frequency compensation capacitor. Its operating supply voltage is 2.5 V, and it has a temperature coefficient of 58.3 ppm/°C and a nominal reference voltage of 1.205 V. Process corner simulations in SS, FF and TT corners are processed accordingly, in parallel with Monte Carlo Analysis, having commendable results. Its PSRR is -84.21 dB in TT corner which indicates good noise immunity from the supply rail to protect its preceding subcircuits.

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