Differential MRAM Sensing Scheme With Magnetoresistance Boosted 4T-2MTJ Bit-Cell

For the increasing demand for energy-efficient computing in edge devices, spin transfer torque magnetic random access memory (STT-MRAM) becomes a promising candidate for next-generation embedded memory, thanks to its high density and nonvolatile. This article proposes a voltage difference boost scheme to enhance the sensing margin under low supply voltage. The sensing circuits consist of two main subcircuits: 1) a novel bit-cell using magnetoresistance boost and 2) a voltage boost sensing amplifier (VB-SA). The VB-SA is an SA based on positive feedback so that the sensing margin is near the voltage supply ( ${V_{\mathrm{ DD}}}$ ). The simulation analysis is performed with a 28 nm process and an STT magnetic tunnel junction (STT-MTJ) compact model. The results show that the power consumption is only 12.2 fJ/bit, which is significantly reduced and the cost of yield loss is negligible.