Signal integrity analysis of 2.5D package with silicon bridge

Against the backdrop of slowing Moore's Law, silicon bridge interconnect technology, as a key solution for heterogeneous integrated packaging, is leading the technological innovation of interconnecting high-performance computing chips. Silicon bridge technology can provide extremely high interconnect density, and compared with traditional substrate interconnects, it can achieve finer pitch (e.g., below 2 microns) and support higher bandwidth data transmission; secondly, the short-distance interconnect of silicon bridges reduces the signal transmission delay and power consumption, and improves the efficiency of inter-chip communication; furthermore, silicon bridges are made of silicon-based materials, which are compatible with the chip fabrication process, and can be integrated into 2.5D packages (e.g., EMIB) Finally, silicon bridges support heterogeneous integration, which facilitates the compact connection of different types of chips (e.g., CPU, GPU, memory), optimises system performance, and allows for the flexible use of different processes, which makes manufacturing less difficult. These features give silicon bridges a significant advantage in HPC, AI and data centre applications. Due to the extremely high wiring on silicon bridges, different designs of silicon bridge structures can have signal integrity effects on ultra-high density signal channels, therefore, it is important to quantitatively assess the signal integrity of various types of parameters in the silicon bridge structure on silicon bridge designs by creating silicon bridge models. In this paper, an in-depth study of the silicon bridge structure and its related parameters on the quality of signal transmission is carried out using the HFSS tool by creating an accurate model and performing extensive simulation analyses, and a corresponding optimisation strategy is proposed. This work will provide important theoretical basis and technical support for the design and fabrication of high-density layout wiring on silicon bridges, and provide theoretical data and reference for silicon bridge design.