多核处理器
芯片上的系统
结温
三维集成电路
炸薯条
互连
堆积
计算机科学
堆栈(抽象数据类型)
集成电路
嵌入式系统
热的
材料科学
并行计算
光电子学
物理
电信
核磁共振
气象学
程序设计语言
作者
Sankatali Venkateswarlu,Subrat Mishra,Herman Oprins,Bjorn Vermeersch,Moritz Brunion,Jun-Han Han,Mircea R. Stan,Dwaipayan Biswas,Pieter Weckx,Francky Catthoor
出处
期刊:IEEE Transactions on Very Large Scale Integration Systems
[Institute of Electrical and Electronics Engineers]
日期:2023-12-01
卷期号:31 (12): 1896-1904
标识
DOI:10.1109/tvlsi.2023.3314135
摘要
Due to the rise in the number of cores in modern multicore architectures, 3-D integration (i.e., vertical stacking of chips) of system-on-a-chip (SOC) promises better performance due to a drastic reduction in global interconnect lengths and die footprint compared with 2-D counterparts. However, thermal issues are predominant in 3-D-SOCs due to the vertical stacking nature of chips which multiplies the transistor power density by the number of dies within the stack. Also, the reduced lateral heat spreading with aggressive die thinning degrades the ON-chip thermal performances. In this article, we investigate the thermal performance analysis of 3-D-SOC and compare the results with the 2-D-SOC designs for a MemPool multicore SOC with shared L1 scratchpad memory (SPM). Simulation results reveal that the 3-D-SOC using memory-on-logic (MOL) configuration increases the ON-chip maximum temperature by more than 20% compared with the baseline 2-D-SOC and the logic die temperature is relatively higher (3.6%) than the memory die. We also explore the impact of architectural floor-planning effects and 3-D functional partitioning on thermal performance of the MemPool instances in the 3-D-SOC with memory capacity ranging from 1 to 8 MiB and benchmarked the thermal performance with the 2-D-SOC designs. We observe that the junction-to-ambient temperature ( $T_{\max }$ ) increases by 44% and is predominant for the SPM capacity of 8 MiB. Further investigations on various 3-D stacking configurations reveal there is an improvement in thermal performance for MOL over logic-on-memory (LOM) for L1 SPM capacity of 1, 2, and 4 MiB, and LOM over the MOL configuration for L1 SPM capacity of 8 MiB.
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