(Invited) Mechanical Stress Simulations for Advanced Logic Devices

Novel transistor concepts are continuously being investigated to scale beyond FinFETs and nanosheets. One such architecture is the Complementary FET (CFET), consisting of an NFET and a PFET fabricated on top of each other [1-4], offering increased device density thanks to its stacking. However, additional challenges arise, such as significantly complicated processing and higher complexity of the connections between devices. Another concern lies in the optimization of the device performance by incorporating mechanical channel strain: in particular for the top-channel device it is challenging to employ traditional stressors efficiently, as it is largely disconnected from the substrate underneath. The purpose of this study is to study whether a CFET technology, and especially its top-channel device can be properly stressed. To this end, a TCAD process simulation flow that mimics the relevant steps for stress modeling has been built using Sentaurus-Process [5]. An example of a quarter-structure of the simulated CFET at the end of the simulation (after channel release) is shown in Fig. 1. The device has a gate length of 14nm, a fin-like silicon channel both for the top and bottom device (5nm width, 30nm height), and fully strained source/drain (S/D) epitaxial layers in the bottom and top devices. For the top (NFET) device, the source/drain epi does not fill up all available space but consists rather of a thin layer grown against the sidewalls of the device, as observed experimentally. Tungsten contacts are added to connect the devices, and a thin oxide layer is present in the source/drain regions to isolate the top from the bottom device. Fig. 2 shows the longitudinal channel stress in the channels for a varying composition of the top-channel S/D epi. A large compressive (i.e. negative) stress is generated in the bottom PFET channels, thanks to the strained Si 0.5 Ge 0.5 bottom S/D epi. On the other hand, the channel stress in the top channel is much smaller and becomes more tensile (positive) for higher Ge% in the top S/D. This opposite trend from traditional S/D’s was reported for nanowires in [6] and can be explained by the fact that the top S/D does not fill up the available space, which leads also to a large reduction in absolute channel stress. Another observation from Fig. 2 is that the stress in the bottom channel is independent of the composition in the top S/D, indicating that the devices are mechanically decoupled. Fig. 3 plots the channel stress in the structure after various steps of the simulation, showing that a small channel stress is generated after S/D etch by the presence of the sacrificial layer (Si 0.75 Ge 0.25 ) between the channels. Furthermore, dummy gate removal tends to increase the absolute channel stress. Finally, the bottom S/D epi growth does not affect the top-channel stress, again confirming the mechanical decoupling of both channels to first order. Fig. 4 shows how the channel stress is affected for an intrinsic tensile stress of 2GPa in the tungsten or oxide isolation between the devices. Tungsten is a rather ineffective stressor due to its high stiffness: less than 200MPa tensile top-channel stress is generated by a stressed tungsten in its S/D’s. For the bottom device, the effect is even smaller due to the increased distance between the bottom-tungsten and the channel. The oxide isolation proves to be a more efficient stressor for the top channel, leading to about 1GPa additional tensile stress which is concentrated at the bottom of the channel. The presentation will highlight the importance of other stress components besides longitudinal stress. Furthermore, whereas the results in Figs. 1-4 were obtained for fin-like (vertically elongated) devices, a CFET technology can also be built using nanosheet (horizontally elongated) channels. It will be shown that changing towards this type of channels leads to a significant change of the stressor effectiveness in CFET technologies. These insights will help us to continue improving the device performance in advanced transistor architectures like CFETs. References [1] W. Rachmady et al, IEDM Tech. Dig., 697 (2019). [2] S. Subramanian et al., VLSI Tech. Dig., TH3.1 (2020). [3] C.-Y. Huang et al, IEDM Tech. Dig., 425 (2020). [4] M. Radosavljevic et al., IEDM Tech. Dig., 721 (2021). [5] Sentaurus Process Reference Manual, Synopsys, M-2016.12 (2016). [6] G. Eneman et al., ECS Trans. 98 (5), pp. 253 (2020) Figure 1