Leakage Current Model of Polycrystalline Silicon Thin-Film Transistors for Device Characterization and Circuit Simulation

Carrier emission due to trap states is considered to be the most important factor influencing the leakage generation of polycrystalline silicon thin-film transistors (poly-Si TFTs). An analytical relation between the field enhanced emission rate ratio and electric field is proposed, which accounts for the Poole–Frenkel effect. The proposed relation needs no numerical integration, and both the relation and its first derivative are continuous, which are critical in circuit simulation. The maximum electric field near the drain is calculated taking density of trap states into account. The leakage current is studied. And its variations with gate and drain voltages are compared with available experimental data. The temperature dependence of leakage current is also shown. The results show an excellent agreement with experimental data.