化学机械平面化
抛光
铜互连
氧化物
材料科学
锡
阻挡层
CMOS芯片
计算机科学
纳米技术
光电子学
图层(电子)
复合材料
冶金
作者
C. Euvrard,A. Seignard,V. Balan,E. Gourvest,S. Gaillard,M. Rivoire
标识
DOI:10.1109/icpt.2014.7017237
摘要
Beyond C14nm, better W CMP performances are required due to new CMOS integration constraints such as contact density increase, wide W feature introduction or low oxide loss for any polishing steps related to gate building. In order to address these new requirements, this paper propose an approach similar to Cu damascene CMP, using three consecutive polishing steps respectively for planarization, selective stop on Ti/TiN barrier and barrier removal. This study discuss advantages and limitations of this approach and points out process improvement obtained among which lower oxide erosion, tunable W recess, better oxide WIWNU and minimized oxide loss.
科研通智能强力驱动
Strongly Powered by AbleSci AI