A Fully Integrated LDO With 50-mV Dropout for Power Efficiency Optimization

This brief presents, a fully integrated low-dropout regulator (LDO) with 50-mV dropout voltage for high power efficiency, with a LDO-self-supplied differential error amplifier (EA) for higher power supply rejection (PSR), and a coupled transient enhancement unit for fast transient response. With 50-mV dropout voltage, the LDO can achieve 94.4% power efficiency in the full load condition. The LDO is fabricated in a standard 28-nm bulk CMOS process with 0.0086-mm2active area. It features a 288-MHz unity-gain bandwidth (UGB) at 20-mA load current, while consuming a quiescent current of 33 μA. With such high bandwidth and the coupled transient enhancement unit, the proposed LDO achieves 270-ps response time for a 0-to-20-mA load transient with 100-ps edge time. The self-supplied EA helps to achieve a PSR of -30 dB even with only 50-mV dropout. The ultra-fast response, small area, and high efficiency features make the proposed LDO very suitable for working as distributed point-of-load regulators in a digital system.