HARNS: High-level Architectural Model of RRAM based Computing-in-memory NPU

As the research on deep neural networks booms, there is broad interest in the accelerator with RRAM-based computing-in-memory architecture to tackle the problem of "memory wall". However, the simulator for large-scale RRAM-based SoC, expected to provide detailed performance analysis, remains unexplored. In this paper, we develop HARNS in C++ and SystemC, an architectural model of RRAM-based neural-processing-unit. HARNS proposes a flexible structure for users to customize the architecture, and provides cycle-accurate performance simulation for design space exploration. A 7-layer convolution network is demonstrated on HARNS, followed by some optimization schemes of architecture and mapping.