神经形态工程学
脑-机接口
电阻随机存取存储器
吞吐量
接口(物质)
计算机科学
分类
横杆开关
尖峰分选
Spike(软件开发)
人工神经网络
计算机硬件
神经科学
并行计算
脑电图
人工智能
工程类
电气工程
电压
操作系统
无线
心理学
电信
软件工程
气泡
最大气泡压力法
程序设计语言
作者
Yuhan Shi,Akshay Ananthakrishnan,Sangheon Oh,Xin Liu,Gopabandhu Hota,Gert Cauwenberghs,Duygu Kuzum
标识
DOI:10.1109/ted.2021.3131116
摘要
Real-time spike sorting and processing are crucial for closed-loop brain-machine interfaces and neural prosthetics. Recent developments in high-density multi-electrode arrays with hundreds of electrodes have enabled simultaneous recordings of spikes from a large number of neurons. However, the high channel count imposes stringent demands on real-time spike sorting hardware regarding data transmission bandwidth and computation complexity. Thus, it is necessary to develop a specialized real-time hardware that can sort neural spikes on the fly with high throughputs while consuming minimal power. Here, we present a real-time, low latency spike sorting processor that utilizes high-density CuOx resistive crossbars to implement in-memory spike sorting in a massively parallel manner. We developed a fabrication process which is compatible with CMOS BEOL integration. We extensively characterized switching characteristics and statistical variations of the CuOx memory devices. In order to implement spike sorting with crossbar arrays, we developed a template matching-based spike sorting algorithm that can be directly mapped onto RRAM crossbars. By using synthetic and in vivo recordings of extracellular spikes, we experimentally demonstrated energy efficient spike sorting with high accuracy. Our neuromorphic interface offers substantial improvements in area (~1000× less area), power (~200× less power), and latency (4.8μs latency for sorting 100 channels) for real-time spike sorting compared to other hardware implementations based on FPGAs and microcontrollers.
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