逐次逼近ADC
比较器
功勋
电容器
塑造
CMOS芯片
电压
计算机科学
电容
偏移量(计算机科学)
电子工程
电气工程
转换器
物理
工程类
电极
光电子学
量子力学
程序设计语言
作者
Chun-Cheng Liu,Soon-Jyh Chang,Guan-Ying Huang,Ying-Zu Lin
出处
期刊:IEEE Journal of Solid-state Circuits
[Institute of Electrical and Electronics Engineers]
日期:2010-04-01
卷期号:45 (4): 731-740
被引量:974
标识
DOI:10.1109/jssc.2010.2042254
摘要
This paper presents a low-power 10-bit 50-MS/s successive approximation register (SAR) analog-to-digital converter (ADC) that uses a monotonic capacitor switching procedure. Compared to converters that use the conventional procedure, the average switching energy and total capacitance are reduced by about 81% and 50%, respectively. In the switching procedure, the input common-mode voltage gradually converges to ground. An improved comparator diminishes the signal-dependent offset caused by the input common-mode voltage variation. The prototype was fabricated using 0.13-¿m 1P8M CMOS technology. At a 1.2-V supply and 50 MS/s, the ADC achieves an SNDR of 57.0 dB and consumes 0.826 mW, resulting in a figure of merit (FOM) of 29 fJ/conversion-step. The ADC core occupies an active area of only 195 × 265 ¿m 2 .
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