抖动
时钟发生器
锁相环
相位检测器
探测器
CMOS芯片
计算机科学
电子工程
功率(物理)
时钟恢复
时钟频率
误码率
时钟信号
电气工程
物理
电压
工程类
电信
频道(广播)
量子力学
作者
Zhao Zhang,Guang Zhu,Can Wang,Li Wang,C. Patrick Yue
标识
DOI:10.1109/a-sscc47793.2019.9056913
摘要
This paper presents a low-power low-jitter PAM4 clock and data recovery circuit. A novel quarter-rate linear phase detector (QLPD) is proposed to lower the recovered clock jitter. A self-biased PLL based multiphase clock generator (MCG) is proposed to reduce power consumption. Fabricated in 40-nm CMOS process, the prototype achieves error-free operation at 32-Gb/s input data rate with 0.46-pJ/bit bit efficiency and 352.6-fs integrated jitter of the 4-GHz recovered clock. The measured jitter tolerance at BER of $ is higher than 0.35 UI PP with the corner frequency at about 10 MHz.
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