A high performance CMOS device with inverter delay 13 ps at 1.2 V power supply

A gate delay 13 ps operating at 1.2 V has been developed for 0.13 /spl mu/m CMOS logic technology application. In this work, the Leff of device is 0.08 um and the inversion oxide thickness is 3.2 nm. NMOS and PMOS transistor drive currents are 630 uA/um and 270 uA/um respectively at Ioff=4 nA/um. The Vt,sat rolloff from the nominal gate length to the worst gate length is about 50 mV for NMOS and 30 mV for PMOS.