重复性
校准
电子线路
计算机科学
模具(集成电路)
工艺变化
电子工程
群时延和相位时延
电压
电气工程
数学
工程类
电信
带宽(计算)
统计
操作系统
作者
Mozhgan Mansuri,Bryan Casper,Frank O’Mahony
标识
DOI:10.1109/vlsic.2012.6243808
摘要
This paper demonstrates an in-situ delay measurement circuit which precisely characterizes key clocking circuits such as full phase rotation interpolators. This on-die all-digital circuit produces a digital output value proportional to the relative delay between two clocks, normalized to the clock period. This circuit requires no calibration for variation or process, voltage, temperature (PVT) and measures the delay with 250fs absolute accuracy and repeatability of 10fs-rms.
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