Test Strategies on Non Volatile Memories Electrical Wafer Sort on NAND, NOR Flash and Phase Change Memories

The increase of integration, density size and logic complexity of non volatile memories (NVM), as NAND-flash, NOR-flash and phase change memory (PCM) require the utilization of expensive and adapted test hardware, due also to the different electrical interfaces. This paper presents a series of design for testability (DFT) solutions, based on customized pin interface, built-in self test (BIST), built-in self redundancy and repairs (BISR&R) to be adopted for a cost-effective use of automatic test equipment (ATE). The main advantage of the proposed test structures is the increment of throughput on installed base.