串行解串
逐次逼近ADC
计算机科学
电气工程
工程类
计算机硬件
电压
电容器
作者
Jun Chen,Fengyi Mei,Mingzhe Liu,Yongzhen Chen,Jiangfeng Wu
标识
DOI:10.1109/asicon58565.2023.10396350
摘要
Wireline receiver front-ends increasingly utilize high-speed time-interleaved ADCs for improved equalization through subsequent digital processing and support for higher-order modulation schemes. A 32GS/s 7bit TI-SAR ADC in 28nm with auto error calibration and trimmed clock is proposed for 32Gb/s ADC-Based SerDes Receiver, achieving stable and high performance with relatively low power consumption. Post-layout simulation results show that the proposed TI-SAR ADC achieves 38.65dB SNDR and 61.41mW power consumption with -1dBFS input signal at Nyquist input frequency.
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