Design analysis and fabrication of FinFET using 3 nm technology

The performance of Fin FET design is the newest technology compared to conventional bulk FinFET and nanowire gate-all-around (GAA) FET, three-dimensional simulations have been done for both n-channel and p-channel transistors. The results of this design (FinFET) provides for improved electrostatic energy relative to the FinFET but less gate capacitance relative to the GAA FET. Therefore, FinFET technology, as an industry, enhances continuous transistor scaling with good performance improvement for low-power system-on-chip various applications. FinFET device has two gates only. There is no effect on the channel from the top gate either, but from the sides only, whereas Trigate is current-controlled from the channel's three sides. In SOI, FinFET, the fin is starting from the oxide surface and gate oxide material. It Means that Bulk and Fin, directly not connected. In bulk FinFET, Fin starts from the wafer, then it moves, and there is sio2. After that, gate oxide material is deposited.