Metal-free high-contrast wafer-level step height standards with large height-range based on all-dielectric multilayers

Abstract Wafer-level step height standards with high optical contrast are crucial in order to improve the accuracy of automatic image recognition in integrated circuits inspection instruments. While conventional Si–SiO 2 single-layer film step height standards typically employ metal coatings to address low contrast issues at low step heights, this approach can be problematic due to the introduction of metal particle contamination. In this paper, we propose a high-contrast wafer-level step height standard based on silicon-on-insulator (SOI) dielectric multilayers. The SOI multilayers, composed of Si–SiO 2 –Si layers are designed to achieve consistent high optical contrast across varying step heights by maximizing reflectance ratio. We designed three step height standards of 20 nm, 100 nm, 500 nm with different SOI multilayers. All were fabricated on 8 inch wafers by merging film deposition, electron-beam lithography and dry etching. The maximum contrast was two orders higher than single-layer film steps of the same height, while maintaining precision in step height measurement. This novel wafer-level step height standards have the potential to enhance image recognition efficiency while mitigating the risk of metal contamination to detection systems and production lines.