A 0.4-V 8400-μm2 Voltage Reference in 65-nm CMOS Exploiting Well-Proximity Effect

This brief exploits, for the first time, the well-proximity effect to develop a sub-0.5 V voltage reference with a high power-supply rejection ratio (PSRR) and a compact area. The layout-dependent effect (LDE) is deemed to affect the matching and characteristics of analog circuits in the deep-submicron CMOS process. Here we explore the LDE effect in designing analog circuits, by exemplifying it with a CMOS voltage reference. Validated in 65-nm CMOS, the voltage reference occupies 8, $400~\mu $ m2 and outputs a reference of 107.2 mV at a $\text{V}_{\mathrm{ DD}}$ of 0.4 V, with a power of 56.7 nW. The temperature coefficient is 79.4 ppm/°C across −20 to 80 °C (average of 12 samples) after a two-point batch trimming and scores a high PSRR of −66.5 dB. The standard deviation of 12 chips is 2.6 mV, evincing the robustness of the voltage reference exploiting the LDE.