A 0.18 /spl mu/m flash source side erasing improvement

The aim of this work is to present two solutions developed to optimize Flash cell erasing time. These solutions have been proposed with our flash simulator based on Pao and Sah approach. This model was implemented in a common circuit simulator, Eldo, and used to study the Flash memory writing/erasing operations. Thank to simulations, we have proposed two solutions to increase injection efficiency of the cell during erasing operation. The first solution is based on signal optimization and the second on a simple process modification during SAS etching. These two solutions have been validated with ST-Microelectronics Flash technologies.