TSV-based Stacked Silicon Capacitor with Embedded Package Platform

In this paper, authors propose a new type of trough silicon via (TSV)-based stacked silicon capacitor (SSC). This SSC is designed by stacking two silicon capacitor wafers, thereby connecting wafers with Cu to Cu bonding. As a result of wafer stack, SSC can have two times of capacitance and lower ESL characteristics when compared with the same size of Conventional Silicon Capacitor (CSC). Furthermore, if we stack n wafers additionally, we will be able to acquire N times of capacitance. In addition, when we adopt this SSC as an embedded capacitor (eCAP) in a cored substrate system on a chip (SoC) package, SSC has the advantage of reducing the distance from bumps to a decoupling capacitor. And we can design two sided bump SSC that allows the area of bottom side of the SSC can be used for power delivery network (PDN) design. Thus, shortcut PDN design through TSV is possible. As a result, the inductance generated in the package is reduced and the Power Integrity (PI) characteristic is improved. Through this work, we provide a comparative study of SSC, conventional silicon capacitor, and conventional ceramic capacitor with a cored substrate platform for premium mobile SoC products. Impedance characteristics and voltage drop simulation experimental results are provided in this paper. Through electrical performance simulation analysis, the effect of the new technology in this work on the performance improvement of the SoC package will be demonstrated through performance measurement evaluation finally.