CMOS芯片
相位检测器
炸薯条
锁相环
探测器
相位频率检测器
电子工程
抖动
物理
计算机科学
算法
电压
电气工程
工程类
电容器
充电泵
电信
作者
Woojung Kim,Woojin Hong,Jae Joon Kim,Myunghee Lee
出处
期刊:IEEE Transactions on Very Large Scale Integration Systems
[Institute of Electrical and Electronics Engineers]
日期:2023-01-01
卷期号:31 (6): 851-860
标识
DOI:10.1109/tvlsi.2023.3266352
摘要
This article proposes a single-loop referenceless clock and data recovery (CDR) with a bilateral bang-bang phase and frequency detector (BBPFD). The CDR achieves an unlimited frequency acquisition range in both directions of the lock frequency. The proposed BBPFD tracks the frequency by using the asymmetry of UP/DN output probability of the bang-bang phase detector (BBPD). A seamless transition between frequency acquisition and phase tracking is possible through a simple modification of the existing BBPD. The CDR has a locking time of 3 $\mu$ s under the PRBS7 pattern. The test chip was fabricated in a 28-nm CMOS process. It supports a 5.4-Gb/s link rate, making it compatible with the embedded DisplayPort (eDP) standard v1.2. The total power consumption is 3.04 mW at a speed of 5.4 Gb/s/lane. The power efficiency is 0.57-pJ/bit at a supply voltage of 0.9 V.
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