Power-Management with Read-Write Assistant Single Port SRAM for Low Power Applications

With the explosive growth of social demand for calculation power and the developing of extensive applications of smart devices loading with the System on Chip(SoC). SRAM occupies a large mount of SoC power consumption. This paper proposes a new structure using in single port SRAM which can implement low-power data storage. The Structure using power management circuit and read-write assistant circuit working together to reduces the power consumption during non read/write period effectively. The read-write assistant circuit can reduce the worst working voltage of SRAM (Vmin) through the capacitor structure. This structure using in single port SRAM Compiler Tape-out by SMIC 14nm FinFET process. Verified the single port SRAM with this structure help SRAM read/write successfully to acquire an excellent power performance. The result tested by ADVANTEST V93000 test platform.