计算机科学
无损压缩
JPEG格式
无损JPEG
图像压缩
JPEG 2000
现场可编程门阵列
计算机硬件
压缩比
有损压缩
加速
硬件体系结构
软件
并行计算
数据压缩
嵌入式系统
图像处理
算法
图像(数学)
人工智能
工程类
汽车工程
程序设计语言
内燃机
作者
Xuan Wang,Lei Gong,Chao Wang,Xi Li,Xuehai Zhou
标识
DOI:10.1109/iccd53106.2021.00060
摘要
The lossless image compression technique has a great application value in distortion-sensitive applications. JPEG-LS, as a mature lossless compression standard, is widely adopted for its excellent compression ratio. Many hardware JPEG-LS compressors are proposed on FPGAs and ASICs to achieve high energy efficiency and low cost. However, JPEG-LS has a contextual Read-After-Write (RAW) issue, making previous hardware either insufficiently explore its parallelism potential or induce other defects while parallelizing, such as compression ratio dropping and compatibility problems. In this paper, we propose a hardware/software co-design method for high-performance JPEG-LS compressor design. At the software level, we propose a pixel grouping scheduling scheme and the Pseudo-LS method to tap the parallelism aiming at the RAW issue. At the hardware level, we discuss the high-performance design methods of these software-level schemes and propose a design space exploration method to constrain the resource usage introduced by parallelization. To our knowledge, our architecture, UH-JLS, is the first pixel-level parallelization streaming image compressor based on the standard JPEG-LS. The experiments show that in the lossless manner and the Pseudo-LS manner, UH-JLS respectively achieves 5.6x and 7.1x speedup than the previous state-of-the-art FPGA-based JPEG-LS compressor.
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