Gate-last vs. gate-first technology for aggressively scaled EOT logic/RF CMOS

We report on gate-last technology for improved effective work function tuning with ∼200meV higher p-EWF at 7A EOT, ∼2x higher f max performance, and further options for channel stress enhancement than with gate-first by taking advantage of the intrinsic stress of metals and gate height dependence. Additional key features: 1) scavenging technique yielding UT-EOT down to ∼5A is demonstrated in gate-last, with high-k deposited first, through the use of an Etch-Stop-Layer with composite nature and similar TDDB reliability to gate-first; 2) controlled alloying for EWF engineering is obtained by careful material selection and tuned metals thicknesses ratio; 3) suppression of abnormal L gate - and W gate -dependence on J G , EOT and NBTI for devices with both high-k and metal deposited last (L gate ≥35nm, W gate ≥80nm) demonstrates the potential for improved UT-EOT control down to small devices with this scheme.