包对包
成套系统
有限元法
电子包装
可靠性(半导体)
芯片级封装
互连
模具(集成电路)
炸薯条
集成电路封装
机械工程
体积热力学
可靠性工程
计算机科学
制造工程
汽车工程
工程类
电子工程
结构工程
电气工程
电信
物理
薄脆饼
功率(物理)
晶片切割
量子力学
作者
Pavan Rajmane,D. Karthikeyan,M. Philip Schwarz,Ahmer Syed
标识
DOI:10.1109/ectc32696.2021.00240
摘要
Rapid growth of electronic devices and increased customer demands for high performance, low cost and miniaturized design has led to increased design complexities and several assembly and reliability issues. Increased customer demand, PCB-package synergies, time to market can often lead to explore advanced package technologies like System-on-Chip (SoC), System-in-Package (SiP) etc. Even with advances in novel package technologies and improved interconnect technologies, need for larger die/package driven by IO needs often leads to warpage and SMT yielding issues. Typically, these thermomechanical challenges have become critical during new product introduction (NPI) and high-volume manufacturing (HVM). Design and testing difficulty, higher cost and low manufacturing yield are some common challenges faced by these large SiP, thus developing a robust Finite Element Analysis (FEA) methodology is of utmost importance. Unlike experimental testing, FEA modeling is a cost-effective and quicker way to assess various factors and interactions on a system in package. A test vehicle with multi-die on a larger SiP package used for this study. Large SiP packages often results in high volume of mold compound, one of the dominant factors affecting the warpage was studied. It is observed that mold volume is dominating the warpage behavior and shape much higher than traditional discrete packages. Due to higher volume and high Coefficient of Thermal Expansion (CTE) of the mold compound, it is very important to characterize material properties thoroughly for FEA simulations. A full range of temperature dependent material properties are measured using Dynamic Mechanical Analyzer (DMA) and Thermo-Mechanical Analyzer (TMA) for mold compound and substrate to capture the precise behavior of the material at each temperature point. This paper aims to demonstrate a FEA approach to improve warpage prediction for multi-chip packages. Full field shadow moiré technique is used to experimentally measure the warpage at the surface of the substrate (dead bug view). This data is then leveraged to calibrate the proposed FEA model. Furthermore, investigation of the importance of different components on SiP in affecting the warpage and determining the components that can be neglected to reduce complexity of the analysis will be discussed. Finally, example case studies will be presented to show the impact of other package design factors using the FEA model.
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