跨导
单层
缩放比例
拓扑(电路)
材料科学
物理
场效应晶体管
光电子学
晶体管
纳米技术
电气工程
数学
量子力学
几何学
工程类
电压
作者
Keshari Nandan,Amit Agarwal,Somnath Bhowmick,Yogesh Singh Chauhan
标识
DOI:10.1109/ted.2021.3119552
摘要
Pentagonal PdSe2 is a promising candidate for layered electronic devices, owing to its high air-stability and anisotropic transport properties. Here, we investigate the performance of p-type FET based on PdSe$_2$ mono-layer using multi-scale simulation framework combining Density functional theory and quantum transport. We find that mono-layer PdSe$_2$ devices show excellent switching characteristics ($<$ 65 mV/decade) for the source-drain direction aligned along both [010] and [100] directions. Both directions also show good on-state current and large transconductance, though these are larger along the [010] direction for a 15 nm channel device. The channel length scaling study of these p-FETs indicates that channel length can be easily scaled down to 7 nm without any significance compromise in the performance. Going below 7 nm, we find that there is a severe degradation in the sub-threshold swing for 4 nm channel length. However, this degradation can be minimized by introducing an underlap structure. The length of underlap is determined by the trade-off between on-state current and the switching performance.
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