材料科学
晶体管
单层
缩放比例
光电子学
电介质
场效应晶体管
栅极电介质
频道(广播)
平面的
纳米技术
电气工程
电压
几何学
数学
计算机图形学(图像)
工程类
计算机科学
作者
Mengmeng Li,Jiebin Niu,Xufan Li,Yue Tian,Chenming Ding,Congyan Lu,Zhenzhong Yang,Rong Huang,Lingfei Wang,He Yan,Ling Li,Ming Liu
标识
DOI:10.1002/adma.202420201
摘要
Abstract The scaling strategy is widely used to achieve much improved performance and reduced cost in a single chip with more devices for field‐effect transistors (FETs) based on Si and state‐of‐the‐art 2D materials. However, the downscaling of polymer FETs with high performance has not been achieved. Here both the body thickness scaling and channel length scaling strategies are employed, and demonstrate a 2.4‐nm‐thick polymer monolayer FET, where the shortest channel length ( L ) of 18 nm is achieved that is comparable to the smallest technology node (≈20 nm) for planar Si FETs. Such short‐channel FETs, with good operational stability and reliability, exhibit only slightly lower field‐effect mobility than the device with micrometer‐long channel, but the on‐state current density reaches 2.4 × 10 −4 A µm −1 . More importantly, a high intrinsic gate delay of 0.79 ps is achieved, while maintaining the on/off current ratio up to 10 9 . Additionally, by increasing the thickness of gate dielectric a remarkable short channel effect is observed, which is in excellent agreement with natural scale length evaluated by the Scale Length Theory.
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