材料科学
单晶硅
硅
光电子学
纳米技术
薄脆饼
基质(水族馆)
纳米线
数码产品
纳米光刻
晶体管
工程物理
制作
电气工程
电压
工程类
地质学
病理
海洋学
替代医学
医学
作者
Wentao Qian,Yifei Liang,Junzhuan Wang,Zongguang Liu,Jun Xu,Linwei Yu
摘要
A low temperature catalytic growth of orderly ultrathin silicon nanowires (SiNWs) is desirable for the construction of monolithic 3D stacked electronics but usually suffers a large diameter fluctuation and a low growth deployment rate (GDR). In this work, the ultra-confined growth dynamics of in-plane solid–liquid–solid SiNWs within narrow groove tracks has been systematically investigated, and a converging-guiding-track strategy is proposed and testified to accomplish 100% GDR of ultra-dense and uniform SiNW array, with diameter and spacing of only Dnw = 22.5±3.5 nm and 25 nm, respectively. Despite a low temperature growth at 350 °C, the SiNWs are found to be all monocrystalline and Si⟨100⟩ oriented, while prototype Schottky barrier tunneling field effect transistors built on the SiNW channels demonstrate a high Ion/off ratio and subthreshold swing of >105 and 197 mV dec−1. This new strategy complements a long-missing key capability of catalytic growth approach to serve a reliable integration technology of ultrafine high quality 1D c-Si channels, without the need of preexisting wafer substrate, for a wide range of 3D electronics, neuromorphic, and logic-in-memory functionalities.
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