| 标题 |
A 28-nm 75-fsrms Analog Fractional-$N$ Sampling PLL With a Highly Linear DTC Incorporating Background DTC Gain Calibration and Reference Clock Duty Cycle Correction |
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| DOI | |
| 其它 |
期刊:IEEE Journal of Solid-State Circuits 作者:Wanghua Wu; Chih-Wei Yao; Kunal Godbole; Ronghua Ni; Pei-Yuan Chiang; et al 出版日期:2019-05-01 |
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(2025-6-4)