| 标题 |
 Electrical Characteristics of the 4F 2 Vertical Gate (VG) DRAM integrated with Bit Line Shielding (BLS) and Back Gate (BG) Transistor |
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| DOI | |
| 其它 |
期刊：2026 IEEE/JSAP Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) 作者：Seung Wan Chu; Junho Cheon; Jinsun Cho; Eunhyup Doh; Jungmin Han; et al 出版日期：2026-06-14 |
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