| 标题 |
A 0.075-pJ/bit, 8-Gb/s, Power-Efficient Echo-Cancellation-Based Hybrid Circuit Topology for Full-Duplex Transceiver |
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| DOI | |
| 其它 |
期刊:IEEE Transactions on Very Large Scale Integration (VLSI) Systems 作者:Prema Kumar Govindaswamy; Raviteja Kammari; Vijay Shankar Pasupureddi 出版日期:2026 |
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(2025-6-4)