Improving Efficiency of Cell-Aware Fault Modeling By Utilizing Defect-Free Analog Simulation

Cell-aware fault models of standard cells are critical for test and diagnosis of cell-internal defects in advanced-node technology. Due to the large number of analog simulation times required during the generation of cell-aware fault models, it takes much time and hardware expense to prepare the full models of a technology library. A systematic method is proposed in this paper to improve the generation efficiency of the cell-aware fault models. Voltage information within standard cells from defect-free analog simulation is extracted and then utilized to filter out unnecessary input patterns for targeted defects, which reduces analog simulation times and improves efficiency. Pattern selection strategies for different kinds of defects are designed and explained separately. 2292 cells from a library are chosen to verify the proposed method. Compared to the non-optimized routine, the average number of faulty simulation patterns for each cell are reduced by 44.9% and the end-to-end generation time is reduced to 46.6%.