材料科学
光电子学
金属浇口
栅氧化层
肖特基势垒
晶体管
泄漏(经济)
随时间变化的栅氧化层击穿
阈值电压
失效模式及影响分析
压力(语言学)
降级(电信)
和大门
逻辑门
电子工程
电气工程
电压
复合材料
工程类
宏观经济学
经济
语言学
二极管
哲学
作者
Abhas Mehta,H. Shichijo,Jungwoo Joh,Chang Juck Suh,Moon J. Kim
出处
期刊:ECS transactions
[Institute of Physics]
日期:2023-09-29
卷期号:112 (2): 9-20
被引量:2
标识
DOI:10.1149/11202.0009ecst
摘要
This work describes the cause-effect-based degradation process of the p-GaN gate in Enhancement-mode (E-mode) GaN High Electron Mobility Transistors (HEMTs) using gate stressing and failure analysis (FA). We found no correlation between time-to-fail and initial gate current (I G0 ). Instead, a higher impact of temperature was found on the gate current of the device (I G ) and time-to-fail at 100 °C. Gate failure at constant voltage stress was a single-stage failure. Under constant current stress, the gate shows a multi-stage failure. The breakdown starts with increased gate current leading to Schottky barrier leakage and finally to catastrophic contact failure. The metal/p-GaN interface at the gate finger becomes the weakest part of the gate stack. Metal/p-GaN interface and surface defects develop as percolation paths acting as leakage sources, and nano-cracks have been observed in the gate cap. FA also shows physical degradation at the metal/p-GaN cap due to electrical stress.
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