Effect of ITC on Boolean functionality of n-type heterojunction vertical TFETs

The objective of this paper is to investigate the effect of interface trap charges (ITC) on Boolean functionality of n-type vertical TFET structure with and without gate overlap (HJ-VTFET-WG and HJ-VTFET-WOG). For this, the logic gates are designed using HJ-VTFET by considering germanium as source material. Our simulations results have shown that two input logic functions such as AND and OR gates can be successfully implemented using HJ-VTFET-WG and HJ-VTFET-WOG structures. The two key concepts are utilized for achieving logic functionality of proposed vertical TFET such as change in gate–source overlap area and appropriate selection of silicon body thickness. Thereafter, the AND and OR functionality are examined using drain current characteristic and energy band diagram of HJ-VTFETs under different trapped charges. With positive ITC, the logic functions have a smaller tunneling width and a larger tunneling width with negative ITC. It is found that positive ITCs can improve device features, whereas, negative ITCs degrade device performance. Further, the electrical performance of HJ-VTFET-WG is less susceptible to interface trap charges than HJ-VTFET-WOG which indicates that the proposed HJ-VTFET-WOG structure is a potential candidate for designing the logic gates for digital application under ITC effect.