Evaluation of C2W hybrid bonding performance with SiO2/SiCN passivation layers at the interface using finite element simulations

Advanced computing applications such as internet-of-things, autonomous driving and artificial intelligence require integrated chips with fine pitch interconnections. Heterogeneous integration (HI) of dissimilar chips with fine pitch interconnections is enabled by Chip-to-Wafer hybrid bonding (C2W-HB) process. To realize this technology, bonding of the die to wafer interfaces should be robust. Hybrid bonding process has been established for the conventional SiO 2 dielectric. However, SiO 2 dielectrics are prone to defect formation at high temperatures (annealing) and pose risk of delamination. SiCN is an alternative dielectric for hybrid bonding, with attractive bonding strength. Evaluation of process and design parameters is required to establish the C2W-HB process with SiCN dielectric at the bonding interface. In this work we performed finite element simulations to evaluate the bonding performance of Cu pad and dielectric (SiO2/SiCN) interfaces for a two-step annealing process. This work guides the process team to select a suitable process window and optimize the bonding process with minimal experimental runs.