降压式变换器
控制理论(社会学)
锁相环
控制器(灌溉)
CMOS芯片
磁滞
沉降时间
比较器
电子工程
瞬态响应
脉冲宽度调制
噪音(视频)
爆炸-爆炸控制
计算机科学
电压
工程类
物理
相位噪声
电气工程
最优控制
阶跃响应
数学
数学优化
农学
控制(管理)
量子力学
人工智能
控制工程
图像(数学)
生物
作者
Yanqi Zheng,Hua Chen,Ka Nang Leung
标识
DOI:10.1109/tvlsi.2011.2156437
摘要
Hysteresis voltage-mode control is a simple and fast control scheme for switched-mode power converters. However, it is well-known that the switching frequency of a switched-mode power converter with hysteresis control depends on many factors such as loading current and delay of the controller which vary from time to time. It results in a wide noise spectrum and leads to difficulty in shielding electro-magnetic interference. In this work, a phase-lock loop (PLL) is utilized to control the hysteresis level of the comparator used in the controller, while not interfering with the intrinsic behavior of the hysteresis controller. Some design techniques are used to solve the integration problem and to improve the settling speed of the PLL. Moreover, different control modes are implemented. A buck converter with proposed control scheme is fabricated using a commercial 0.35-μ m CMOS technology. The chip area is 1900 μm × 2200 μm. The switching frequency is locked to 1 MHz, and the measured frequency deviation is within ±1%. The measured load transient response between 160 and 360 mA is 5 μ s only.
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