Silicon carbide power MOSFET technology

4H-SiC UMOSFETs and DMOSFETs have been fabricated and tested with measured blocking voltages (1400 V and 900 V, respectively). Although these breakdown voltages were reasonable, obtaining sufficient channel mobility (50 cm/sup 2//Vs) to enable devices with practical current densities has thus far proven elusive owing to the poor quality of the SiC-SiO/sub 2/ interface. DMOS structures suffer from a non-self aligned process, and gate oxide present over rough implanted and annealed SiC surfaces. Thus surface scattering effects and interface state density remain high, lowering carrier mobility. In addition, UMOS devices also suffer from poor inversion layer mobility due to the difficulties of forming high quality oxide on the sidewalls of the vertical trenches. In this paper we will explore these and other design and processing trade-offs.