A Low-Cost Comparator-Based Method for Accurate Decomposition of Deterministic Jitter in High-Speed Links

Jitter decomposition is a key tool to identify root causes of jitters in a high-speed digital communication system. It is a huge challenge in balancing the test cost and precision for conventional decomposition methods implemented in instruments where the time interval error (TIE) data are necessary. In this paper, we propose a deterministic jitter decomposition method using Boolean output from a network of simple low-cost comparators to identify the deviation of current sampling position from the ideal sampling position instead of TIE data. The new method simultaneously separates intersymbol interference (ISI), periodic jitter (PJ), and duty cycle distortion (DCD). Simulation and measurement results demonstrate that the proposed method can estimate the ISI, PJ, and DCD with sufficient accuracy using significantly fewer data samples than the state-of-the-art instrument test, and thus, reduce test cost greatly. Furthermore, the comparators have extremely relaxed design requirements, offering potential for possible on-chip implementation for built-in self-test or background test.