Impact of Common-Emitter Parasitic Inductance on the Turn-on Characteristics of IGBT

During the turn-on transient of insulated gate bipolar transistors (IGBTs), the collector-emitter voltage (VCE) "bump" phenomenon is frequently observed. This voltage spike is characterized by an initial rapid drop in the VCE due to the presence of parasitic inductance, followed by a subsequent rise and fall of VCE as the collector current (IC) increases. This VCE bump critically exacerbates the IGBT turn-on losses (Eon). By analyzing the dynamic variation of dIC/dt during the turn-on process, this study reveals that suppressing the VCE bump fundamentally requires mitigating the initial negative variation of dIC/dt, which originates from interference between the power loop and the gate-signal loop induced by common-emitter parasitic inductance. A step-by-step approach was employed to decouple these loops by adjusting the positioning of the emitter signal terminals, thereby systematically reducing the common-emitter parasitic inductance. Experimental results demonstrate that minimizing common-emitter parasitic inductance effectively enhances the turn-on speed and reduces turn-on losses. When devices with identical turn-on speeds were compared, smaller common-emitter parasitic inductance correlated with a weaker VCE bump. Specifically, the study reveals that a reduction of 1 nH in common-emitter parasitic inductance decreases the Eon by approximately 0.1%.