A Layout Used in Power Modules to Improve Current Imbalance of Parallel SiC MOSFETs

As load demands increase, SiC power modules are widely used due to their low parasitic parameters and high power density. However, due to parasitic inconsistencies, the current cannot be evenly distributed between parallel MOSFETs, which degrades the performance of the power module and may damage the device. Especially the parasitic inductance at the source end. In order to weaken the influence of source parasitic inductance on current sharing, Kelvin-Source connection is widely used. However, the difference in source parasitic inductance outside the driving circuit can still have a great impact on current distribution, this paper proposes a layout structure used in half-bridge SiC power modules to improve the source parasitic inductance difference caused by unreasonable layout. Simulation results show that the proposed new layout can reduce the degree of current imbalance from 37.2% to 16.9% under the traditional layout.