A O.96pJ/b 7 × 50Gb/s-per-Fiber WDM Receiver with Stacked 7nm CMOS and 45nm Silicon Photonic Dies

Emerging applications such as machine learning, high-performance computing, and cloud storage continue to push compute demands at the data center. To keep up, distributed computing architectures are being increasingly adopted where the physical locations of the CPU, GPU, FPGA, memory, and storage may span over several meters. In package silicon-photonics-based optical links with wavelength division multiplexing (WDM) and non-return-to-zero (NRZ) signaling provides a power-efficient, high-bandwidth, and low-latency interface between these components. In this paper, we present a low-power (0.96pJ/b), high-sensitivity (−11.1dBm median), high-bandwidth$(7\times 50\mathsf{Gb}/\mathsf{s}$NRZ WDM) receiver (RX) that achieves <1e-12 bit-error-rate (BER) without forward-error-correction (FEC).