11.10 A 12V-lnput 1V-1.8V-Output 93.7% Peak Efficiency Dual-Inductor Quad-Path Hybrid DC-DC Converter

拓扑(电路) 计算机科学 电容器 物理 算法 电气工程 电压 工程类
作者
Wen‐Liang Zeng,Guigang Cai,Chon-Fai Lee,Chi‐Seng Lam,Yan Lu,Sai‐Weng Sin,Rui P. Martins
出处
期刊: 卷期号:: 10-12 被引量:20
标识
DOI:10.1109/isscc42615.2023.10067710
摘要

A high-efficiency $12\mathrm{V}$ -input $1\mathrm{V}-1.8\mathrm{V}$ -output DC-DC converter with wide output current range is highly desirable in energy-efficient portable devices (e.g., laptops) and automotive applications. $\text{In}$ such applications, the considerably small duty ratio $\mathrm{D}(\mathrm{D} < 0.1)$ and power switches' high voltage stress of the conventional buck converter brings significant efficiency penalty (Fig. 11.10.1, top left). Both industry and academia have developed many hybrid DC-DC converter topologies to overcome these problems [1–6]. The double step-down (DSD) converter, shown in Fig. 11.10.1 (top right), is the most popular solution [2–4] for this application. $\text{In}$ the DSD converter, the flying capacitor $\mathrm{C}_{\mathrm{F}}$ sustains half of $\mathrm{V}_{\text{IN}}$ , relaxing the voltage stress of the switches to $\mathrm{V}_{\text{IN}}/2$ and enlarging the duty ratio D. However, the two inductors must provide all the output current, thus leading to a large inductor DCR loss. To reduce such loss, [5] proposed a dual-path hybrid buck $(2\text{PHB})$ converter (Fig. 11.10.1, bottom left), in which the flying capacitor $\mathrm{C}_{\mathrm{F}}$ sustains the voltage $\mathrm{V}_{\text{OUT}}$ and provides an additional output current path. However, the small duty ratio and switches' high voltage stress problems are still significant in the $2\text{PHB}$ converter. To further enlarge the duty ratio and reduce the voltage stress of the switches, this paper proposes a dual-inductor quad-path hybrid buck $(2\mathrm{L}4\text{PHB})$ converter, as presented in Fig. 11.10.1 (bottom right). The 2L4PHB inherits the strengths of DSD and $2\text{PHB}$ converter topologies, where the flying capacitor $\mathrm{C}_{\mathrm{F}0}$ sustains half of $\mathrm{V}_{\text{IN}}$ , thus relaxing the voltage stress of the switches. $\text{In}$ addition, both $\mathrm{C}_{\mathrm{F}1}$ and $\mathrm{C}_{\mathrm{F}2}$ sustain the voltage $\mathrm{V}_{\text{OUT}}$ and provide additional output current paths, subsequently further reducing the inductor DCR loss. Among the structures shown in Fig. 11.10.1, it has the largest $\mathrm{D} ($ VCR $=\mathrm{D}/2(1+\mathrm{D})$ , VCR $< 1/6)$ , the smallest average inductor current $(\mathrm{i}_{\text{L,avg}}=\mathrm{i}_{\text{Load}}/2(1+\mathrm{D}))$ , and the smallest voltage stress of the switches $(\mathrm{V}_{\mathrm{X}1,2}=0\ \text{or}\ \mathrm{V}_{\text{IN}}/2-\mathrm{V}_{\text{OUT}})$ when compared with the different topologies mentioned above. Furthermore, $2\mathrm{L}4\text{PHB}$ also owns inherent inductor current balance characteristic.
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