A high-speed CMOS preamplifier-latch comparator

A preamplifier-latch CMOS comparator especially for high-speed ADCs is described in this paper. It consists of a preamplifier, a latch stage and output buffer. The proposed comparator separates preamplifier from the positive feedback latched comparator so as to reduce the influence of the kickback noise. Simulation results based on standard CMOS 0. 35μm technology show that, this comparator can achieve 30μV sensitivity while only 0. 6 mW power dissipation at 40 MHz.