电镀
铜
过程(计算)
材料科学
冶金
计算机科学
纳米技术
图层(电子)
操作系统
作者
Wei Ruan,Lan Chen,Zhigang Li,Tianchun Ye,Tianyu Ma,Qiang Wang
出处
期刊:Journal of Semiconductors
[IOP Publishing]
日期:2011-05-01
卷期号:32 (5): 055010-055010
被引量:2
标识
DOI:10.1088/1674-4926/32/5/055010
摘要
The non-planarity of a surface post electroplating process is usually dependent on variations of key layout characteristics including line width, line spacing and metal density. A test chip is designed and manufactured in a semiconductor foundry to test the layout dependency of the electroplating process. By checking test data such as field height, array height, step height and SEM photos, some conclusions are made. Line width is a critical factor of topographical shapes such as the step height and height difference. After the electroplating process, the fine line has a thicker copper thickness, while the wide line has the greatest step height. Three typical topographies, conformal-fill, supper-fill and over-fill, are observed. Moreover, quantified effects are found using the test data and explained by theory, which can be used to develop electroplating process modeling and design for manufacturability (DFM) research.
科研通智能强力驱动
Strongly Powered by AbleSci AI